 VLSI Design Laboratory - Department of Electrical and Computer Engineering Univeristy of Patras Patras, 261 10 Greece Tel: +30-61-997283, 997340 FAX: +30-61-994798 E-mail: goutis@ee.upatras.gr |
|
1 Education :
| 1961-66 : | B.Sc. in Physics, Grade: very good (equivalent to Honours 2.1), University of Athens |
| 1970-72 : | Professional Diploma in Electronic Engineering, University of Athens, part-time |
| Oct. 1973-Oct. 1974 : | M.Sc. in Digital Techniques in Communications and Control, Heriot-Watt University |
| 1974-1978 : | Ph.D., "Constrained optimisation algorithms for digital image reconstruction", Southampton University |
2 Career resume :
| Oct. 1966-67 : | National Service. |
| Nov. 1967-Oct. 1970 : | Teaching in a Tutorial School, preparing candidates for the University entrance examinations. |
| Nov. 1970-Dec. 1972 : | Lecturer, School of Physics and Mathematics, University of Athens. |
| Jan. 1973-Sept. 1973 : | Technical Manager in the Greek Post Office (Telecommunications) responsible for the installation and maintenance of the telephone exchanges in a provincial region having one hundred and sixty personel. This post involved considerable administrative and technical responsibility. |
| July 1976-May 1977 : | Research Assistant in the Department of Electronic and Electrical Engineering, University of Strathclyde, U.K., working on Power Spectrum Analysis for target detection from Pulse Doppler Radar Data. |
| Oct. 1977-Aug. 1979 : | Research Fellow in the Department of Electronic and Electrical Engineering, University of Strathclyde, U.K., working on Image Processing (SERC grant). |
| Sept. 1979-May 1985 : | Lecturer in the Department of Electrical and Electronic Engineering, University of Newcastle upon Tyne, U.K. |
| June 1985-1989 : | Associate Professor in the Department of Electrical Engineering, University of Patras, Greece. |
| Sept. 1989-today : | Professor in the Department of Electrical Engineering, University of Patras, Greece. |
3 Teaching experience :
Prof. Goutis has taught the following courses: Communications, Microprocessors, Electronics for communications, General Electronics, VLSI design, Signal processing, supervision of approximately sixty (60) Part III Projects.
4 Postgraduate supervision :
Supervision of twenty (20) Ph.D. students working in the fields: signal and image processing, VLSI design, system design, parallel processors, analysis and design of systems for signal and image processing.
5 Industrial collaboration :
He has extensively collaborated with a large number of companies, such as British Gas, Joyce Loeble Ltd, doing research and development, during the period he was working in Britain. His group in the VLSI Design Laboratory in Patras University has closed collaboration with Industry. The collaboration includes design of a number of ASICs for Greek companies and a low-power DSP processor for hearing aids for a Danish company through the HEAR Esprit project.
6 Professional activites outside the university
:
| a. | Greek representative in RACE (E.U. R&D Program in Communications) (1989-91). |
| b. | Member of National Committee for Research and Development (Department of Industry, GSRT). |
| c. | Proposal evaluator for the i. Greek Department of Industry (GSRT) ii. Greek Department of Finance (evaluating technical proposals) iii. E.U. in basic research proposals |
| d. | Member of the IEE professional groups U.K. (1983-85) |
| e. | He has chaired sessions in International Conferences. |
| f. | Member of IEEE and charter engineer. |
| g. | Referee for International Journals. |
7 Research interests :
Low-power VLSI design, VLSI design, system design, parallel processors, analysis and design of systems for signal and image processing. Prof. Goutis is working on low-power design methodologies and designs since four years ago. At the logic level, a power estimator exploiting temporal and spatial correlation which is four times faster, while keeping the accuracy, was introduced. Recently, his interests give emphasis to the higher level of design i.e. architectural and algorithm with emphasis to DSP and communication applications. An algorithm reducing the activity whenever data is known a priori e.g. Filter coefficient, matrices, was introduced. Memory management is currently his main research interest.
8 VLSI Design Laboratory :
He has created and developed this Laboratory earning competitive research and development projects. Currently the Laboratory has twenty researchers.
9 Research and development grants :
Fifteen R&D projects from the European Commission and eight from Greek sources. The total amount of grants is about 4 MECUs.
10 Publications :
He has published 191 papers in international journals and conferences:
1. Durrani T.S. and. Goutis C.E, "Multi-dimensional image reconstruction from projections using constraint optimisation", IEE Symposium on current trends in digital image processing, Portsmouth Polytechnic, March, 1976.
2. Goutis C.E. and Durrani T.S., "Recursive algorithms for digital reconstructions of images from their projections", IEE International Conference on Information Science and Systems, Patras, Greece, August 1976.
3. Durrani T.S. and Goutis C.E., "Fourier domain techniques for digital image reconstruction from their projections" in "Digital image processing and analysis" Editors J.C. Simon and A. Rosenfeld, Noordholf, Publ., E20, pp. 93-99, 1977.
4. Goutis C.E. and Durrani T.S., "Digital image reconstruction by circulant like algorithms", Proc. of IERE Conf. on Digital Processing of Signals in Communications, Loughborough, IERE, Conf. Proc., No. 37, pp. 285-292.
5. Taylor R.G., Durrani T.S. and Goutis C.E., "Block processing on pulse Doppler Radar", Proceedings of IEE Con. Radar 77, Savoy Place, UK, pp. 134-140, 1977.
6. Goutis C.E. and Durrani T.S., Report on "High resolution techniques for radar data processing", AT/2065/029 ASWE Contract, June 1977.
7. Goutis C.E. and Durrani T.S., "New algorithms for image reconstruction from fan beam projections" in "Pattern recognition and signal processing" Ed. C.H. Chen, Sijthoff and Noordholf publ., pp. 505-519, 1978.
8. Goutis C.E. and Durrani T.S., "Constraint optimisation techniques for fan beam projection imaging", Proc. of University of Patras/IEEE Conf. "Applications of Information and Control Systems", Edited by D.E. Lainiotis and N.S. Tzannes, Reidel Publication Netherland, pp. 29-37, 1980.
9. Durrani T.S. and Goutis C.E., "Optimisation techniques for digital image reconstruction from their projections", IEE Proc.- Computers and Digital Techniques, Vol. 127, No. 5, pp. 161-169, 1980.
10.Durrani T.S. and Goutis C.E., "A new class of algorithms for digital tomographic reconstruction", IEE Colloquium on "Tomographic Reconstruction Techniques", London, pp. 5.1-2, 6th May 1981.
11.Goutis C.E. and Durrani T.S., "Constrained optimisation algorithms for divergent ray Tomography", IEEE Trans. on Nuclear Sci., v. NS-28, No. 4 pp. 3620-3627, 1981.
12.Goutis C.E., Allen C.R. and Ibrahim M.K., "Speeding up Fougere's algorithm and its VLSI implementation", Proc. of Internat. Conf. on Spectral Analysis and its Use in Underwater acoustics, Institute of Acoustics, Imperial College, England, pp. 15.1-9, April 1982.
13.Goutis C.E. and Durrani T.S., "An optimal technique for tomographic image reconstruction from curved ray projections", ICASSP - 82, pp. 1549-1552, April 1982.
14.Goutis C.E. and Durrani T.S., "Tomographic algorithms for general line integrals", IEEE Trans. Nucl. Sci. vol. NS-29 No. 5, pp. 1399-1404, Nov. 1982.
15.Goutis C.E., Leahy R.M. and Drosos S.N., "Reconstruction algorithms for limited view projection data", ICASSP-83, pp. 143-146, April 1983.
16.Goutis C.E. and Durrani T.S., "Orthogonal transformations for tomographic reconstructions", IEE colloquium on "Transform Techniques in Image Processing", Savoy Place, pp. 8.1-4, May 1983.
17.Goutis C.E. and Ibrahim M.K., "A new algorithm for spectrum estimation and an associated VLSI design", IEE Proc., Part F, Vol. 130, No. 3, pp. 250-255, April 1983.
18.Goutis C.E., Ibrahim M.K. and Cassidy P.G., "Maximum likelihood spectra for non Toeplitz measured covariance matrices", published in Proc. of MECO, 6th IASTED International Symposium, Athens, pp. 198-201, Aug. 1983.
19.Goutis C.E. and Drosos S.N., "A fast reconstruction algorithm for reconstruction from divergent ray projections", IEE Proc. Part. E, Vol. 131, pp. 89-96, 1984.
20.Leahy R.M., Goutis C.E. and Drosos S.N., "Tomographic and spectral analysis using noise statistics”, in Proc. ICASSP-84, pp. 4.3.1-4, USA.
21.Goutis C.E., Leahy R.M. and Cassidy P.G., "Spectra using data distribution and covariance modelling", in Proc. ICASSP-84, pp. 31.7.1-4, USA.
22.Leahy R.M. and Goutis C.E., "Knowledge based spectral estimation using modelling", Proc. of the Intern. Conference on Radar, Paris, pp. 374-379, May 1984.
23.Leahy R.M. and Goutis C.E., "Tomographic and spectral analysis. A unified approach", Intern. Conf. on Signal Porcessing, DSP-84, Florence, pp. 149-151, 1984.
24.Goutis C.E., "Special purpose processor for block circulant sparse matrices with elliptical structure", in Digital Techniques in Simulation, Communications and Control, North Holland, pp. 207-212, 1985.
25.Goutis C.E., Ibrahim M.K. and Leahy R.M., "Optimisation for convolution Kernels with an application to detection of burried pipes", Intern. Conf. on Digital Processing of Signals in Communications, Loughborough, England, April 1985.
26.Makhlouf M.A.R., Goutis C.E., Yung C.H. and Allen C.R., "Concurrent VLSI architecture for covariance-lattice computations in maximum entropy spectrum estimation", Intern. Conf. on Digital Processing of Signals in Communications, Loughborough, England, April 1985.
27.Sheblee J.S. and Goutis C.E., "A processor for linear systems for block circulant sparse matrices", on VLSI Special Purpose Computers and Applications, pp. 8.1-4, London, Feb. 1985.
28.Ibrahim M.K. and Goutis C.E., "Detection algorithm using prediction error-additive noise orthogonality and noise covariance characteristics", in Proc. ICASSP-85, pp. 17.8.1-4, USA.
29.Goutis C.E. and Sheblee J.S., "A 2-D array processor having a controlled pipeline architecture for elliptically sparse matrices", in Proc. ICASSP-85, pp. 36.9.1-4, USA.
30.Yung C.H. and Goutis C.E., "Recursive methodology and VLSI parametrised modules for signal processing", presented in CAVE Workshop, Chester, England, Dec. 1985.
31.Leahy R.M. and Goutis C.E., "Optimal techniques for constraint based signal restoration and image reconstruction", in Proc. ICASSP-85, pp. 18.4.1-4, USA.
32.Goutis C.E., "Unified dual optimisation and algorithms for image recinstruction and spectral estimation", invited paper in Mathematics and Computers in Simulation, Vol. 27, pp. 623-634, 1985.
33.Goutis C.E. and Sheblee J.M., "Design, simulation and layout of an array processor for matrix manipulation", presented in CAVE Workshop, Belgium, May 1985.
34.Drosos S.N. and Goutis C.E., "Fast algorithms for positron emission tomography", appeared in Melecon '85, Spain.
35.Leahy R. M. and Goutis C.E., "An Optimal Technique for Contraint-Based Image Restoration and Reconstruction", IEEE Trans. on ASSP, Vol. ASSP-34, No. 6, pp. 1629-1642, 1986.
36.Goutis C.E. and Blionas S.V., "Array Processor for solving noisy Toeplitz systems", in Proceedings of Conference in Integrated Circuits Technology I, Limerick, Ireland, pp. 65-72, 1986.
37.Goutis C.E., Birbas M.K., Kyriakis-Bitzaros E.D. and Soudris D.J., "Rule-Based Mapping of Iterative Primitives on Their Architectures", CAVE Workshop, Beligrate, Milano, Italy, December 1988.
38.Koufopavlou O.G., Goutis C.E., Nikolaidis S. and Vallidras K., "Integrated Circuits to Control PWM-Power Inverters", presented in two-day conference of Technical Chamber of Greece "Power Electronics, Production-Application-Education", Athens, Greece, February 1989.
39.Mourjopoulos J.N., Kyriakis-Bitzaros E.D. and. Goutis C.E, "Theory and Real-Time Implementation of Time Varying Digital Audio Filters", 86th AES Convention, preprint 2773(R-S), Hamburg, Germany, March 1989 and Journal of the Audio Engineering Society, Vol. 38, No. 7-8, pp. 523-536, 1990.
40.Kyriakis-Bitzaros E.D. and Goutis C.E., "An Efficient Decomposition Technique for Mapping Uniform Recurences onto Regular Array Processors", Int. Workshop on Algorithms and Parallel VLSI Architectures, France, Part B, pp. 94-100, June 1990.
41.Birbas M.K., Soudris D.J. and Goutis C.E., "A New Method for Mapping Iterative Algorithms on Regular Arrays", Proceedings of Bilkent International Conference on New Trends on Communications, Control and Signal Processing, Vol. II, pp. 1121-1127, Ankara, Turkey, July 1990.
42.Birbas M.K,, Soudris D.J. and Goutis C.E., "A New Method for Mapping Matrix Computation Algorithms on Regular Processor Arrays", PARCELLA'91, International Workshop on Parallel Processing by Cellular Automata and Arrays, Berlin, Germany, 17-21, 1990.
43.Metafas D.E. and Goutis C.E., "A DSP Processor with a Powerful Set of Elementary Arithmetic Operations Based on CORDIC and CCM Algorithms", Journal of Microprocessing and Microprogramming 30, pp. 51-58, 1990.
44.Birbas M.K., Soudris D.J. and Goutis C.E., "Modelling and Direct Mapping of Iterative Algorithms on Regular Processor Arrays", Proceedings of International Workshop on Algorithms and Parallel VLSI Architecture, Vol. II, pp. 83-88, Pont-a-Mousson, France, 1990.
45.Kyrloglou N.A., Koufopavlou O.G. and Goutis C.E., "A Generator for a Number Format Conversions IC", Journal of Microprocessing and Microprogramming 30, pp.237-240, 1990.
46.Soudris D.J., Poechmueller P., Kyriakis-Bitzaros E.D., Birbas M.K., Goutis C.E., Glessner M., "Design Methodology for Systematic Derivation of Fault-Tolerant Array Processors", presented in CompEuro'90.
47.Soudris D.J., Birbas M.K. and Goutis C.E., "Design Methodology for Mapping Iterative Algorithms on Piecewise Regular Processor Arrays", Proceedings of CompEuro'91, pp.373-377, Bologna, Italy, May 13-16, 1991.
48.Soudris D.J., Birbas M.K. and Goutis C.E., "Design Methodology for Mapping of Nested Loops on Array Architectures", CAVE Workshop, Agia Pelaghia, Heraklion Greece, May 22-24, 1991.
49.Horianopoulos S.L., Metafas D.E., Goutis C.E. and Deliyannis T., "A Delta Modulation FIR Filter High Level Synthesis Tool", CAVE Workshop, Agia Pelaghia, Heraklion, Greece, May 22-24, 1991.
50.Nikolaidis S., Koufopavlou O.G., Theodoridis S. and Goutis C.E., "An Array Processor for LS FIR System Identification", Proceedings of EUROMICRO'91, Vienna, Austria, pp.557-564 and Microprocessing and Microprogramming 32, pp. 557-564, 1991.
51.Birbas M.K., Kyriakis-Bitzaros E.D., Soudris D.J. and Goutis C.E., "Direct Mapping of Nested Loops and Efficient Decomposition on Uniform Recurrences for Implementation on Array Architectures", Algorithms and Parallel VLSI Architectures, Editor Deprettere, North-Holland, pp.343-352, 1991.
52.Soudris D.J., Birbas M.K., Koufopavlou O.G., Metafas D.E., Nikolaidis S.S., Goutis C.E. and Theodoridis S., "All-Digital Spectrum Analyzer Based on a Parallel Algorithm", Proceedings of IEEE MELECON'91, Ljubljana, Jugoslavia, pp. 408-411, May 22-24, 1991.
53.Soudris D.J., Birbas M.K. and Goutis C.E., "Direct Mapping of Nested Loops on Piecewise Regular Processor Arrays", Proceedings of International Workshop on Algorithms and Parallel VLSI Architectures II, Chateau de Bonas, France, pp. 145-150, June 3-6, 1991.
54.Birbas M.K., Soudris D.J. and Goutis C.E., "Design Methodology for Mapping Iterative Algorithms on Array Architectures", Proceedings of ISCAS, Singapore, pp. 3058-3061, June 1-14, 1991.
55.Kyriakis-Bitzaros E.D. and Goutis C.E., "A New Partitioning Method for Mapping Uniform Recurrences into Fixed Size Processor Arrays", Proceedings of the Fourth ISMM International Conference on Parallel and Distributed Computing and Systems, USA, pp. 39-40, 1991.
56.Horianopoulos S.L., Metafas D.E., Goutis C.E. and Deliyannis T., "A Delta Modulation FIR Filter High Level Synthesis Tool", Proceedings of the Fourth ISMM International Conference on Parallel and Distributed Computing and Systems, USA, pp. 95-99, 1991.
57.Metafas D.E., Krikis G. and Goutis C.E., "VLSI Design of an 8-Bit Fixed-Point CORDIC Processor with Extended Operation Set", Proceedings of EURO ASIC'91, Paris, pp. 158-161, May 27-1, 1991.
58.Metafas D.E. and Goutis C.E., "A Floating Point Pipeline CORDIC Processor with Extended Operation Set", Proceedings of ISCAS'91, Singapore, pp. 3066-3069, June 11-14, 1991.
59.Nikolaidis S.S., Mourjopoulos J.N. and Goutis C.E., "A Processor Architecture for Time-Varying Digital Audio Filters", presented in the International Conference on DSP Applications and Technology, Berlin, October 1991.
60.Soudris D.J., Birbas M.K., Goutis C.E., "Mapping Iterative Algorithms on Regular Processor Arrays without Using Uniform Recurrent Equations", Journal of Microprocessing and Microprogramming 31, pp. 53-58, 1991.
61.Koufopavlou O.G., Kyrloglou N.A., and Goutis C.E., "A Parametric Area, Automated Adder/Subtractor VLSI Design", International Journal of Electronics, Vol. 70, No. 1, pp. 35-42, 1991.
62.Koufopavlou O.G., Metafas D.E. and Goutis C.E., "Architectures and VLSI Module Generator for Expressing Digital Signals in Decibels", International Journal of Electronics, Vol. 71, No.2, pp. 297-307, 1991.
63.Kyrloglou N.A., Koutroubinas S., Koyandis A., and Goutis C.E., "A Placing and Routing Tool Implemented in Prolog", Microprocessing and Microprogramming 32, pp.425-434, 1991.
64.Blionas S.V., Stravrakakis G.N. and Goutis C.E., "Dynamic Source Parameters of the 1981 Gulf of Corinth (Central Greece) Earthquake sequence Based on FFT and Iterative Maximum Entropy Techniques", Tectonophysics, Vol. 3, No.4, pp.261-275, 1991.
65.Kyrloglou N.A., Koutroubinas S., Kogiadis A., and Goutis C.E., "Artificial Inteligence and Integrated Circuits Design", Third Panhellenic Conference on Informatics, Athens, May 1991 (In Greek).
66.Kyrloglou N.A., Koufopavlou O.G. and Goutis C.E., “Number Format Conversion – Algorithm and VLSI Module Generator”, International Journal of Electronics, Vol. 73, iss. 1, pp. 145-156, 1992
67.Horianopoulos S.L., Metafas D.E., Goutis C.E. and Deliyannis T., "A VLSI Synthesis Tool for Complementary Output Delta Modulation FIR Filters", Journal of Microprocessing and Microprogramming 34, pp. 139-142,1992.
68.Kyriakis-Bitzaros E.D. and Goutis C.E., "An Efficient Decomposition Technique for Mapping Nested Loops with Constant Dependencies into Regular Processor Arrays", Journal of Parallel and Distributed Computing, 16, Academic Press, pp.258-264, 1992.
69.Kyrloglou N.A., Koufopavlou O.G. and Goutis C.E., "ASCARID: A Standard Cell Automated Design Rule Independent Module Generator Environment", Journal of Microcomputer Applications, 15, pp. 103-119, 1992.
70.Kyriakis-Bitzaros E.D. and Goutis C.E., "A Systematic Partitioning Method for Designing Fixed-Size Processor Arrays", Journal of Circuits, Systems and Computers, Vol. 2, No. 1, pp. 75-80,1992.
71. Soudris D.J., Poechmueller P., Kyriakis-Bitzaros E.D., Birbas M.K., Goutis C.E., Glesner M., “Design Methodology for Systematic Derivation of Fault-Tolerant Array Processors”, CompEuro 1992, pp. 562-567, 1992.[JCK1]
72.Nikolaidis S.S., Mourjopoulos J.N., and Goutis C.E., "A Processor for Time-Varying Digital Audio Filters with Special Transition Properties", 4th Euromicro Workshop on Real Time Systems, Athens, pp. 15-20, June 3-5, 1992.
73.Koufopavlou O.G. and Goutis C.E., "Image Reconstruction on a Special Purpose Array Processor", Image and Vision Computing Vol. 10, No. 7, pp. 479-484, September 1992.
74.Metafas D.E., Nikolaidis S.S. and Goutis C.E., "Real Time Cepstrum Computation Based in an Advanced CORDIC Processor", Microprocessing and Microprogramming 37, pp. 57-60, 1993.
75.Metafas D.E., Mariatos E., Nicolaidis S.S. and Goutis C.E., "Implementaion of Given's Rotation Processors for DSP Real-Time Applications", presented in Euromicro '93 and Journal of Microprocessing and Microprogramming 38, pp. 351-357, 1993.
76.Economou G.-P., Nikolaidis S.S., Metafas D.E., and Goutis C.E., "Development of a Technology Independent Library", presented in Euromicro '93 and Journal of Microprocessing and Microprogramming 39, pp. 241-244, 1993.
77.Nikolaidis S.S., Mourjopoulos J.N., Goutis C.E., "A Dedicated Processor for Time-Varying Digital Audio Filters", IEEE Transactions on Circuits and Systems II, Vol. CAS-40, pp. 452-455, July 1993.
78.Nikolaidis S.S., Metafas D.E., and Goutis C.E., "CORDIC Based Pipeline Architecture for All-Pass Filters", IEEE Proceedings of ISCAS'93, Vol 3/4, pp.1917-1920, 1993.
79.Soudris D.J., Paliouras V., Stouraitis T., Skavantzos A., and Goutis C.E., "Systematic Design of Full Adder-Based Architectures for Convolution", IEEE Proceedings of ICASSP'93, Vol. I/V, pp. 389-392, 1993.
80.Economou G.-P. K., Nikolaidis S.S., Metafas D.E., Goutis C.E., "Technology Independent Library For Fast Turn-Arround ASIC Design", Proceedings of 4th EUROCHIP Workshop in VLSI Design Training, Toledo, Spain, pp. 356-361, Sept.-Oct. 1993.
81.Kyriakis-Bitzaros E.D., Koufopavlou O.G. and Goutis C.E., "Space-Time Representation of Iterative Algorithms and the Design of Regular Processor Arrays", International Conference on Parallel Processing, Vol.III, pp. 2-9, 1993.
82.Dre C., Tatsaki A., Stouraitis T. and Goutis C.E., "A Novel Prime Factor Algorithm for the 1-D and 2-D Discrete Cosine Transform", Proceedings of European Conference on Circuit Theory and Design (ECCTD'93), Davos, pp. 797-802 , August 1993.
83.Kyriakis-Bitzaros E.D., Koufopavlou O.G. and Goutis C.E., “Space-Time Representation of Iterative Algorithms and the Design of Regular Processor Arrays”, IBM Research Report, RC 19000, May 1993.
84.Kyriakis-Bitzaros E.D., Koufopavlou O.G. and Goutis C.E., “Space-Time Representation of Iterative Algorithms and the Design of Regular Processor Arrays”, Proceedings of the International Conference on Parallel Processing, St. Charles, Illinois, USA, Volume III, pp. 2-9, August 16-20, 1993.
85.Hallas J.A., Birbas M.K., Kikidis J.C., Birbas A.N. and Goutis C.E., “Near-Lossless Compression of Continuous-Tone Still Images Using Fuzzy Logic notions and the Binary Arithmetic Coder (Q-Coder)”, Proceedings of ISCAS'94, London, UK, Vol. 3/6, pp. 125-128, 1994.
86.Mariatos E., Metafas D.E., Hallas J.A. and Goutis C.E., “A Fast D.C.T. Processor, Based on Special Purpose CORDIC Rotators”, Proceedings of ISCAS'94, London, UK, Vol. 4/6, 271-274, 1994.
87.Hallas J.A., Mariatos E.P., Birbas M.K., Birbas A.N. and Goutis C.E., “A CAD tool for the development of an Extra-Fast Fuzzy Logic Controller based on FPGAs and memory modules”, Proceedings of FPL'94, Prague, Chech Republique, 1994.
88.Paliouras V., Kyriakis-Bitzaros E.D., Stouraitis T. Goutis C.E., “Modelling of Algorithms and Processor Arrays Based on Cellllular Automata”, Modelling Techniques and Tools for Computer Performance Evaluation 1994, Vienna, pp. 63-66, May 1994.
89.Economou G.-P.K., Anagnostopoulos G.C. and Goutis C.E., “Experiences Accumulated by the Simulation of an Application Specific Analog Integrated Circuit”, 5th Eurochip Workshop on VLSI Design Training, Dresden, Germany, pp. 406-411, October 1994.
90.Tatsaki A., Stouraitis T. and Goutis C.E., “An Efficient Pyramid VQ‑based Image Compression Algorithm”, IEEE Data Compression Conference (DCC'94), Snowbird Utah, pp.479, March 1994.
91.Dre C., Gianopoulou S. and Goutis C.E., “A Fast Algorithm for Vector Quantization Codebook Generation”, SPIE VCIP'94, Chicago USA, Vol. SPIE 2308, pp. 199‑208, September 1994.
92.Tatsaki A. and Goutis C.E., “A Bit‑Serial VLSI Architecture for the 2‑D Discrete Cosine Transform”, Euromicro'94, Liverpool, England, 1994 and Journal of Microprocessing and Microprogramming, North-Holland, Vol. 40, pp. 829-832, 1994.
93.Dre C., Branis G. and Goutis C.E., “Image Compression using Vector Quantization of Wavelet Coefficients", Euromicro'94, 4‑9 September 1994, Liverpool, England and Microprocessing and Microprogramming 40, pp. 927-930, 1994.
94.Economou G.-P. K., Anagnostopoulos G.C., Theofilou D.T., Stouraitis T. and Goutis C.E., “Non-Linear Optimization: Artificial Neural Network Solution Techniques Applied to the Optimum Linear Feedback Control of Linear Discrete-Time Dynamic Systems”, 20th Euromicro Conference: System Architecture and Integration, Liverpool, U.K., pp. 637-643, September 1994.
95.Economou G.-P.K., Spiropoulos C., Economopoulos N.M., Charokopos N., Lymberopoulos D., Spiliopoulou M., Haralambopoulou C. and Goutis C.E., “Medical Diagnosis and Artificial Neural Networks: A Medical Expert System Applied to Pulmonary Diseases”, 1994 IEEE International Workshop on Neural Networks for Signal Processing, Ermioni, Greece, pp. 482-489, September 1994.
96.Economou G.-P.K., Mariatos E.P., Economopoulos N.M., Lymberopoulos D., and Goutis C.E., “FPGA Implementation of Artificial Neural Networks: An Application on Medical Expert Systems”, 4th International Conference on Microelectronics for Neural Networks and Fuzzy Systems, Torino, Italy, pp. 287-293, September 1994.
97.Economou G.-P.K., Spiropoulos C., Economopoulos N.M., Charocopos N., Lymberopoulos D., Spiliopoulou M., Haralambopulu C. and Goutis C.E., “Medical Decision Making Systems in Pulmonology: A Creative Environment based on Artificial Neural Networks”, 1994 IEEE Conference on Systems, Man and Cybernetics: Humans, Information and Technology, San Antonio, USA, pp. 975-980 ,October 1994.
98.Economou G.-P.K. ., Spiropoulos C., Economopoulos N.M., Charokopos N., Zikos P., Lymberopoulos Dand Goutis C.E., “Decision Supporting Systems in Medical Diseases’ Diagnosis: An Artificial Neural Networks Approach”, 1994 Annual Fall Meeting of the Biomedical Society, Tempe, Arizona, 14-16/10/1994.
99.Economou G.-P.K., Economopoulos N.M., Charokopos N., Zikos P., Lymberopoulos D., Spiropoulos C. and Goutis C.E., “Suggesting Diagnosis of Diseases and Treatment: How Far Artificial Neural Networks Can Go?”, 1994 IEEE ISANN, Tainan, Taiwan, 15-17/12/1994.
100.Economou G.-P.K., Economopoulos N.M., Lymberopoulos D. and Goutis C.E., “Experiences Accumulated towards Medical Decision Support Systems”, J. of Microprocessing and Microprogramming, vol. 40, pp. 883-886, 1994.
101.Nikolaidis S., Theodoridis S., Goutis C.E., “Array Processor for Brock Adaptive LS FIR Filtering”, Signal Processing (North Holland), Vol. 39, pp. 215-222, 1994.
102.Tatsaki A., Burekas B. and Goutis C.E., “An Efficient Bit‑Serial VLSI Implementation of the 4x4‑point Discrete Cosine Transform”, International Journal of Electronics, Vol. 77, No. 2, pp. 259-267, 1994.
103.Psychalinos C. and Goutis C.E., “Improved Switched-Current (Si) Bilinear Integrator Circuit”, IEE Electronics Letters, Vol. 31, No. 1, pp. 26-27, 1995.
104.Economou G.-P., Lymberopoulos D. and Goutis C.E., “An ANNs-based System for the Diagnosis and Treatment of Diseases”, Neural Processing Letters, Vol. 2, No. 1, pp. 22-26 , January 1995.
105.Tatsaki A., Dre C., Stouraitis T. and Goutis C.E., “Prime Factor DCT Algorithms”, IEEE Transactions on Signal Processing, Vol. 43, No. 3, pp. 772-776, March 1995.
106.Tatsaki A., Dre C., Stouraitis T. and Goutis C.E., “On the Computation of the prime factor 1‑D discrete sine transform” Journal Signal Processing North‑Holland Publications, vol 42, No. 3, pp. 231-236, 1995.
107.Tatsaki A., Stouraitis T. and Goutis C.E., “Image Coder Based on Residue Number System for Progressive Transmission”, IEE Electronics Letters, Vol. 31, No. 6, pp. 442-443, March 1995.
108.Dre C., Tatsaki A. T., Stouraitis T., Goutis C.E., "Alternative Architectures for the 2-D DCT Algorithm", IEEE International Symposium on Circuits and Systems (ISCAS'95), pp. 2156-2159, March 1995.
109.Tatsaki A., Stouraitis T., and Goutis C.E., “A Progressive Image Compression Scheme based on Lattice Vector Quantization”, presented in EUROPTO, The European Symposium on Advanced Networks and Services, Compression Technologies and Standards for Image and Video Communications, Amsterdam, March 1995.
110.Dre C. and Goutis C.E., “An Efficient Address‑Vector‑Quantization based Image Coding Scheme”, presented in EUROPTO, The European Symposium on Advanced Networks and Services, Compression Technologies and Standards for Image and Video Communications, Amsterdam, March 1995.
111.Economou G.-P., Hallas J.A., Mariatos E. and Goutis C. E., “Artificial Neural Networks in Medical Decision Making Systems: An Application to Pulmonary Diseases Diagnosis through VHDL Synthesis”, presented in the European Design and Test Conference, Paris, France, 6-9/3/1995.
112.Dre C., Alexopoulou N., Goutis C.E., "Multi-stage Hierarchical Address Vector Quantization for Image Coding", International Journal of Electronics, vol. 78, no. 5, pp. 865-872, May 1995.
113.D.J. Soudris, P.D. Georgakopoulos, and C.E. Goutis, "A Systematic Methodology for Designing Multilevel Array Architectures", Inter. Journal of Electronics, vol. 79, no. 5, pp. 507-518, 1995.
114.Dre C., Lafruit G., Stouraitis T., Cornelis J. and Goutis C.E., "Chinese Remainder Theorem‑based Algorithm for Convolution," Proc. IEEE International Conference on Digital Signal Processing 1995, vol. 1, pp. 255-260, Cyprus, June 26-28, 1995.
115. Metafas and C.E. Goutis, "A Floating Point Advanced Cordic Processor", Journal of VLSI Signal Processing, Vol. 10, pp. 53-65, 1995.
116.L. Bisdounis, G. Panagiotaras, O. Koufopavlou, C. E. Goutis, “CMOS Multi-input Gate Implementations for Low-Power Digital Design”, International Journal of Electronics, vol. 79, no. 5, pp. 641-653, November 1995.
.
117.L. Bisdounis, S. Nikolaidis, O. Koufopavlou, C. E. Goutis, “Modeling the CMOS Short-Circuit Power Dissipation”, Proc. IEEE International Symposium on Circuits & Systems, vol. 4, pp. 469-472, May 1996.
118.Kyriakis-Bitzaros E.D., Soudris D.J. and Goutis C.E., “Transformation of Nested Loops into Uniform Recurrences and Their Mappings to Regular Processor Arrays”, Journal of Circuits, Systems and Computers, Vol. 6, No.3, pp. 243-265, World Scientific Publ. Cp., 1996.
119.Masselos K., Merakos P., Stouraitis T., Goutis C. E., “Low-Power Image Decoding using Fractals”, IEEE International Conference on Electronics Circuits and Systems (ICECS’96), Rhodes, Greece, Vol. II, pp. 748-751, October 1996.
120.Theodoridis G., Theoharis S., Soudris D., Koufopavlou O. and Goutis C.Ε., "A Novel Approach for Reducing the Switching Activity in Two Levels Circuits", International Conference on Electronics, Circuits and Systems (ICECS' 96), Rhodes, Greece, vol. II, pp. 840, October 1996.
121.Bisdounis L., Nikolaidis S., Koufopavlou O., Goutis C.E., "Accurate Timing Model for the CMOS Inverter", IEEE International Conference on Electronics, Circuits and Systems (ICECS’96), Rhodes, Greece, vol. I, pp. 89-92, October 1996.
122.Soudris D., V. Paliouras, T. Stouraitis, and C.E. Goutis, "A VLSI Design Methodology for RNS Full Adder-Based Inner Product Architectures”, IEEE Transactions on Circuits and Systems II, Vol. 44, No. 4, pp. 315-318, April 1997.
123.Masselos K., Merakos P. M., Stouraitis T., Goutis C. E., “Novel Codebook Design Techniques for Vector Quantization Image Compression”, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Hong-Kong, Vol. II, pp. 1321-1324, June 1997.
124.Merakos P. K., Masselos K., Koufopavlou O., Nikolaidis S. and Goutis C. E., “A Novel Transformation for Reduction of Switching Activity in FIR Filters Implementation”, IEEE International Conference on Digital Signal Processing (DSP’97), Santorini, Greece, Vol. II, pp. 653-656, July 1997.
125.Theoharis S., Theodoridis G., Soudris D. and Goutis C.Ε., “A new method for switching activity estimation of logic level networks”, 7th Int. Workshop of European Project Power And Timing Modeling Optimization and Simulation (PATMOS’97), pp. 131-140, September 1997.
126.Masselos K., Merakos P., Stouraitis T., Goutis C. E., “Low-Power Image Coding using a Block Transformation”, IEEE International Conference on Electronics Circuits and Systems (ICECS’97), Cairo, Egypt, Vol. III, pp. 1067-1071, December 1997.
127. Masselos K., Merakos P. Stouraitis T., Goutis C. E., “Trade-Off Analysis of a Low-Power Image Coding Algorithm”, Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, Special Issue on Systematic Trade-Off Analysis in Signal Processing Systems Design, Kluwer Academic Publishers, Vol. 18, No. 1, pp. 65-80, January 1998.
128.Bisdounis L., Nikolaidis S., Koufopavlou O., Goutis C.E., "Switching response modeling of the CMOS inverter for sub-micron devices", in Proc. IEEE Design, Automation and Test in Europe Conference (DATE 98) Paris, France, pp. 729-735, February 1998.
129.Soudris D., Poechmueller P., Kyriakis-Bitzaros E.D., Birbas M., Goutis C.E. and Thanailakis A., “Design Methodology for systematic derivation of fault-tolerant processor array architectures”, International Journal of Electronics, vol. 84, no. 6, pp. 615-624, Taylor & Francis, 1998.
130.Masselos K., Stouraitis T., Goutis C. E., “Novel Codebook Generation Algorithms for Vector Quantization Image Compression”, 1998 IEEE International Conference on Acoustics Speech and Signal Processing (ICASSP’98), Seattle, Washington, USA, Vol. V, pp. 2661-2664, May 1998.
131.Masselos K., Merakos P., Stouraitis T., Goutis C. E., “A Novel Methodology for Power Consumption Reduction in a Class of DSP Algorithms”, IEEE International Conference on Circuits and Systems (ISCAS’98), Monterey, California, USA, Vol. VI, pp. 199-202, June 1998.
132.Zervas N.D., Masselos K., Goutis C.E., "Code Transformations for Embedded Multimedia Applications: Impact on Power and Performance", Power Driven Microarchitecture Workshop of ISCA'98, Barcelona, Spain, pp. 20-24, June 1998.
133.Masselos K., Merakos P., Stouraitis T., Goutis C. E, “A Novel Algorithm for Low Power Image and Video Coding”, IEEE Transactions on Circuits and Systems for Video Technology, Vol. 8, No. 3, pp. 258-263, June 1998.
134.Masselos K., Merakos P., Stouraitis T., Goutis C.E., “Low Power Implementation of Discrete Wavelet Transform”, IX European Signal Processing Conference (EUSIPCO’98), Rhodes, Greece, Vol. II, pp. 869-872, September 1998.
135.Theoharis S., Theodoridis G., Soudris D. and Goutis C.Ε., “Accurate Data Path Models For RT-Level Power Estimation”, 8th Int. Workshop of European Project Power And Timing Modeling Optimization and Simulation (PATMOS’98), pp. 213-222, September 1998.
136.Theodoridis G., Theoharis S., Soudris D., and Goutis C.Ε., “Method for Minimizing the Switching Activity of Two-Level Logic Circuits”, IEE Proceedings on Computers & Digital Techniques, Vol. 145, No. 5, pp. 357-363, September 1998.
137.Masselos K., Stouraitis T., Goutis C. E., "Novel Scheme for Low-Power Classified Vector Quantization Image Coding", IEE proceedings on Vision, Image and Signal Processing, Vol. 145, No. 6, pp. 408-414, December 1998.
138.Masselos K., Merakos P., Stouraitis T., Goutis C. E., “Novel Vector Quantization Based Algorithms for Low-Power Image Coding and Decoding”, IEEE Trans. On Circuits and Systems II, Vol. 46, No. 2, pp. 193-198, February 1999.
139.Theodoridis G., Theoharis S., Soudris D., and Goutis C.Ε., “A New Method for Low Power Design of Two Level Logic Circuits”, VLSI Design Journal, Vol. 9, No. 2, pp. 147-157, 1999.
140.Masselos K., Catthoor F., Goutis C. E., DeMan H., "Interaction between Sub-word Parallelism Exploitation and Low Power Code Transformations for VLIW Multi-media Processors", IEEE Alessandro Volta Memorial Workshop on Low Power Design, Como, Italy, pp. 52-60, March 1999.
141.Masselos K., Merakos P., Stouraitis T., Goutis C. E., "Low Power Synthesis of Sum-Of-Product Computation in DSP Algorithms", 1999 IEEE International Conference on Circuits and Systems (ISCAS’99), Orlando, Florida, USA,Vol. VI, pp. 420-423, May-June 1999.
142.Zervas N. D., Masselos K., Koufopavlou O., Goutis C. E., "Power Exploration of Multimedia Applications Realized on Embedded Cores", 1999 IEEE International Conference on Circuits and Systems (ISCAS’99), Orlando, Florida, USA, Vol. IV, pp. 378-381, May-June 1999.
143.Perakis M., Tzimas A.E., Metaxakis E.G., Soudris D., Kalivas G.A., Katis C., Dre C., Goutis C.E., Thanailakis A. and Stouraitis T., “The VLSI Implementation of a Baseband Receiver for DECT-Based Portable Applications”, 1999 IEEE International Conference on Circuits and Systems (ISCAS’99), Orlando, Florida, USA, Vol. I, pp. 198-201, May-June 1999.
144.Theodoridis G., Theoharis S., Soudris D., Goutis C.E., “An Efficient Probabilistic Method for Logic Circuits Using Real Delay Gate Model”, 1999 IEEE International Conference on Circuits and Systems (ISCAS’99), Orlando, Florida, USA, Vol. I, pp. 286-289, May-June 1999.
145.Danckaert K., Masselos K., Catthoor F., DeMan H., Goutis C.E., “Strategy for Power Efficient Design of Parallel Systems”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 7, No. 2, pp. 258-265, June 1999.
146.Masselos K., Danckaert K., Catthoor F., Goutis C. E., DeMan H., "A Methodology for Power Efficient Partitioning of Data-dominated Algorithm Specifications within Performance Constraints", IEEE International Symposium Low-Power Electronics and Design, San Diego, USA, pp. 270-272, August 1999.
147.Kyriakis-Bitzaros E.D., Goutis C.E., “A Space-Time Representation Method of Iterative Algorithms for the Design of Processor Arrays”, Journal of VLSI Signal Procesing, Kluwer Academic Publishers, Vol. 22, No. 3, pp. 151-162, September 1999.
148.Masselos K., Catthoor F., Goutis C. E., DeMan H., “System-Level Power Optimizing Data-Flow Transformations For Multimedia Applications Realized On Programmable Multimedia Processors”, 1999 IEEE Conference on Electronics Circuits and Systems (ICECS’99), Paphos, Cyprus, pp. III1733-III1736, September 1999.
149.Karaolis E., Nikolaidis S., Goutis C.E., “Fault Secure Binary Counter Design”, 1999 IEEE Conference on Electronics Circuits and Systems (ICECS’99), Paphos, Cyprus, pp. 1659-1662, September 1999.
150.Kakaroudas A.P., Papadomanolakis K., Karaolis E., Nikolaidis S., Alahiotis N., Goutis C.E., “Hardware and Power Requirements of Self-Checking Circuits”, 1999 IEEE Conference on Electronics Circuits and Systems (ICECS’99), Paphos, Cyprus, pp. 1655-1658, September 1999.
151.Kakaroudas A.P., Papadomanolakis K., Karaolis E., Nikolaidis S., Goutis C.E., “Hardware/Power Requirements Versus Fault Detection Effectiveness in Self-Checking Circuits”, International Workshop on Power, Timing, Modeling, Optimization and Simulation (PATMOS’99), Kos, Greece, pp.387-396, October 1999.
152.Masselos K., Catthoor F., Goutis C. E., DeMan H., "Code Size Effects of Power Optimizing Code Transformations for Embedded Multimedia Applications", International Workshop on Power, Timing, Modeling, Optimization and Simulation (PATMOS’99), Kos, Greece, pp. 61-70, October 1999.
153. Zervas N. D., Masselos K., Goutis C. E, "Data-Reuse Exploration for Low-Power Realization of Multimedia Applications on Embedded Cores", International Workshop on Power, Timing, Modeling, Optimization and Simulation (PATMOS’99), Kos, Greece, pp. 71-80, October 1999.
154.Theoharis S., Theodoridis G., Zervas N.D., Goutis C.E., “Accurate and Fast Power Estimation of Large Combinational Circuits”, International Workshop on Power, Timing, Modeling, Optimization and Simulation (PATMOS’99), Kos, Greece, pp. 199-208, October 1999.
155. Masselos K., Catthoor F., Goutis C. E., DeMan H., "A Performance-Oriented Use Methodology of Power Optimizing Code Transformations for Multimedia Applications Realized on Programmable Multimedia Processors", IEEE Workshop on Signal Processing Systems, Taiwan, pp. 261-270, November 1999.
156. Masselos K., Merakos P., Stouraitis T., Goutis C.E., “Novel Techniques for Bus Power Consumption Reduction in Realizations of Sum-of-Product Computation”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 7, No. 4, pp. 492-497, December 1999.
157. Masselos K., Merakos. P., Stouraitis T., Goutis C.E., “Low Power Architectures for Digital Signal Processing”, Journal of Systems Architecture, Elsevier Publlishers B.V., Vol. 46, Issue 7, pp. 551-571, March 2000.
158. Masselos K., Merakos. P., Stouraitis T., Goutis C.E., “Computation Reordering: A Novel Transformation for Low Power DSP Synthesis”, VLSI Design Journal, Gordon and Breach Science Publishwers SA, Vol. 10, No. 2, pp. 177-202, 2000.
159. Soudris D., Zervas N. D. et al., "On the Low Power Design of Digital Receivers for Wireless Applications", in Proc. of Design Automation and Test in Europe (DATE) – User Forum, Paris, France, pp. 255-259, March, 2000.
160. Zervas N. D., Soudris D., Theoharis S., Goutis C. E. and Thanailakis A., "A Methodology for the Behavioral-Level Event-Driven Power Management of Digital Receivers", in Proceedings of Int. Symp. οn Circuits & Systems (ISCAS'2000), Vol. II, pp. 589-592, Geneva, Switzerland, May 2000.
161. Soudris D., Perakis M., Mizas X., Mardiris V., Katis K., Dre C., Tzimas A., Metaxakis E., Kalivas G., Zervas N., Theoharis S., Theodoridis G., Thanailakis A. and Goutis C., "Low-Power Design of a Multi-Mode Tranceiver", in Proceedings of Int. Symp. on Circuits & Systems (ISCAS'2000), Vol. II, pp. 721-724, Geneva, Switzerland, May 2000.
162. Theoharis S., Theodoridis G., Merakos P.K. and Goutis C.E., “Accurate Data Path Models for Fast RT-Level Power Estimation”, IEE Proceedings-Computers and Digital Techniques, Vol. 147, No. 4, pp. 209-214, July 2000.
163. Masselos K., Theoharis S. Merakos P.K., Stouraitis T. and Goutis C.E., “Low-Power Synthesis of Sum-of-Products Computation”, Proceedings of ISPLED 2000, pp.234-237, Rapallo, Italy, July 2000.
164. Zervas N.D., Perakis M., Soudris D., Dre C., Goutis C.E. and Thanailakis A., “A Low-Power GMSK/GFSK MoDem”, 3rd Intern. Workshop ESDLPD 2000, pp. 135-144, Rapallo, Italy, July 2000.
165. Theodoridis G., Theoharis S., Zervas N.D. and Goutis C.E., «Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions», Proceedings of 2000 IEEE Intern. Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS’2000), Gottingen, Germany, pp. 76-87, Sept. 2000.
166. Zervas N.D., Theoharis S., Kakarudas A.P., Soudris D. and Goutis C.E., «Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers», Proceedings of 2000 IEEE Intern. Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS’2000), Gottingen, Germany, pp. 46-55, Sept. 2000.
167. Kakarudas A.P., Papadomanolakis K., Kokkinos V. and Goutis C.E., «Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance», Proceedings of 2000 IEEE Intern. Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS’2000), Gottingen, Germany, pp. 187-194, Sept. 2000.
168. Soudris D., Zervas N.D., Argyriou A., Dasygenis M., Tatas K., Goutis C.E., Thanailakis A., “Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications”, Proceedings of 2000 IEEE Intern. Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS’2000), Gottingen, Germany, pp. 243-254, Sept. 2000.
169. Masselos K., Danckaert K., Catthoor F., Zervas N., Goutis C.E. and De Man H., “A Specification Refinement Methodology for Power Efficient Partitioning of Data-Dominated Algorithms Within Performance Constraints”, Journal of VLSI Signal Processing 26, Kluwer Academic Publishers, Vol. 26, No. 3, pp. 291-317, November 2000.
170. Theodoridis G., Theoharis S., Soudris D. and Goutis C.E., “Switching Activity Estimation Under Real-Gate Delay Using Timed Boolean Functions”, IEE Proceedings Comp.Digit. Techn., Vol. 147, No.6, November 2000.
171. Theodoridis G. Theoharis S., Soudris D., Goutis C.E., “A Probabilistic Power Estimation Method for Combinational Circuits Under Real Gate Delay Model”, in VLSI Design, Journal of Custom-Chip Design, Simulation and Testing, Taylor & Francis, Vol. 12, No. 1, pp. 69-79 (invited paper), 2001.
172. Theodoridis G. Theoharis S., Soudris D., Goutis C.E., “A Fast and Accurate Method of Power Estimation for Logic Level Networks”, in VLSI Design, Journal of Custom-Chip Design, Simulation and Testing, Taylor & Francis, Vol. 12, No. 2, pp. 205-219 (special issue on Low-Power Design), 2001.
173. Zervas N.D., Spiliotopoulos V., Anagnostopoulos G., Goutis C.E., Soudris D., “Performance Comparison of DWT Scheduling Alternatives on Programmable Platforms”, in Proc. Intern. Symposium on Circuits and Systems (ISCAS) 2001, May 6-9, Sydney, Australia, pp. vol. II 761-764, 2001.
174. Andreopoulos Y., Schelkens P. Zervas N.D., Stouraitis T., Goutis C.E. and Cornelis J., “A Wavelet-Tree Image-Coding System with Efficient Memory Utilization”, in IEEE 2001 International Conference on Acoustics, Speech and Signal Processing (ICASSP’ 2001), Salt Lake City, Utah, May 2001.
175. Spiliotopoulos V.G, Zervas N.D., Anagnostopoulos G.P. and Goutis C.E., “Quantization Effect on VLSI Implementations for the 9/7 DWT Filters”, IEEE 2001 International Conference on Acoustics, Speech and Signal Processing (ICASSP’ 2001), Salt Lake City, Utah, May 2001.
176. Liveris N., Zervas N.D., Kakarountas A.P. and Goutis C.E., "A Code Transformation-Based Methodology for Improving I-Cache Performance", in Proc. of 8th IEEE International Conference on Electronics, Circuits and Systems (ICECS'01), Malta, Vol.II, pp.917-920, Sept. 2001.
177. Masselos K., Catthoor F., Kakarountas A.P., Goutis C.E., DeMan H., "Memory Hierarchy Layer Assignment for Data Re-Use Exploitation in Multimedia Algorithms Realized on Predefined Processor Architectures", in Proc. of 8th IEEE International Conference on Electronics, Circuits and Systems (ICECS'01), Malta, vol.I, pp.285-288, Sept. 2001.
178. Kakarountas A.P., Kokkinos V. and Goutis C.E., "Design of Low-Power On-Line Reconfigurable Datapaths Using Self-Checking Circuits", in Proc. of 8th IEEE International Conference on Electronics, Circuits and Systems (ICECS'01), Malta, vol.III, pp.1565-1568, Sept. 2001.
179. Papadomanolakis K., Kakarountas A.P., Kokkinos V., Sklavos N. and Goutis C.E., "The Effect of Fault Secureness in Low-Power Multiplier Designs", in Proc. of 2001 IEEE International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS'01), Yverdon-Les-Bains, Switzerland, pp. 10.3, Sept. 2001.
180. Masselos K., Catthoor F., Goutis C.E., DeMan H., “Effect fo Data Transfer and Storage Optimization on Design Quality Factors of Multimedia Algorithms Realized on Instruction Set Processors”, in Proc. of 2001 IEEE International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS'01), Yverdon-Les-Bains, Switzerland, pp. 3.3.1-3.3.10, Sept. 2001.
181. Andreopoulos Y., Zervas N.D., Lafruit G., Schelkens P., Stouraitis T., Goutis C.E., Cornelis J., “A Local Wavelet Transform Implementation Versus an Optimal Implementation of the Row-Column Algorithm for the Multilevel Binary-Tree Decomposition of Images”, in IEEE Intern. Conference on Image Processing (ICIP) Thessaloniki, Greece, October 2001.
182. Kroupis N., Dasigenis M., Argyriou A., Tatas K., Soudris D., Thanailakis A., Zervas N.D., Goutis C.E., “Power, Performance and Area Exploration of Block Matching Algorithms Mapped on Programmable Processors”, in IEEE Intern. Conference on Image Processing (ICIP) Thessaloniki, Greece, pp. 728-731, October 2001.
183. Papadomanolakis K., Kakarountas A.P., Kokkinos V., Sklavos N. and Goutis C.E., "A Comparative Study on Fault Secure Signed Multiplication Designs", in Proc. of 11th IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC'01), Montpellier, France, pp. 183-188, Dec. 2001.
184. Zervas N.D., Anagnostopoulos G.P., Spiliotopoulos V., Andreopoulos Y. and Goutis C.E., “Evaluation of Design Alternatives for the 2-D-Discrete Wavelet Transform”, IEEE Transactions on Circuits and Systems for Video Technology, Vol. 11, No. 12, pp. 1246-1262, December 2001.
185. Zervas N.D., Perakis M., Soudris D.J., Metaxakis E.G., Tzimas A., Kalivas G.A., Goutis C.E., “Low-Power Design of Direct Conversion Baseband DECT Receiver”, IEEE Transactions on Circuits and Systems-II, Vol. 48, No. 12, pp. 1121-1131, December 2001.
186. Liveris N., Zervas N.D., Soudris D., Goutis C.E., “A Code Transformation-Based Methodology for Improving I-Cache Performance of Multimedia Applications”, in Proceedings of Design Automation & Test in Europe (DATE) 2002, Paris, pp.977-983, March 4-8, 2002.
187. Kakarountas A.P., Papadomanolakis K.S., Nikolaidis S., Soudris D., Goutis C.E., “Confronting Violations of the TSCG(T) in Low-Power Design”, Intern. Symposium on Circuits and Systems (ISCAS) 2002, 26-29 May, Scottsdale, Arizona, USA, 2002.
188. Merakos P., Masselos K., Goutis C. E., "Power Efficient Hierarchical Scheduling for DSP Transformations", VLSI Design Journal, Gordon and Breach Science Publishers SA. (To appear)
189. Zervas N. D., Masselos K., Karayiannis Y. A., Goutis C.E, "Energy Minimization under Area and Performance Constraints for Multimedia Applications Realized on Embedded Cores", VLSI Design Journal, Gordon and Breach Science Publishers SA. (To appear)
190. Masselos K., Catthoor F., Goutis C. E., DeMan H., “A Systematic Methodology for the Application of Data Transfer and Storage Optimizing Code Transformations for Power Consumption and Execution Time Reduction in Realizations of Multimedia Algorithms on Programmable Processors”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems. (To appear)
191. Masselos K., Theoharis S., Merakos P., Stouraitis T., Goutis C. E., "Memory Accesses Reordering for Interconnect Power Reduction in Sum-of-Products Computations", IEEE Transactions on Signal Processing. (To appear)
Chapters in Books
1. Soudris D.J., Kyriakis-Bitzaros E.D., Paliouras V.R., Birbas M.K., Stouraitis T. and Goutis C.E., "On the Design of Two-Level Pipelined Processor Arrays", in Application Driven Architecture Synthesis, (eds) F. Catthoor and L .Svensson, Kluwer Academic Publishers, Ch.5, pp. 95-116, 1993.
2. Masselos K., Goutis C.E., “Power Efficient Synthesis of Sum-of-Products Computations”, Chapter in “Unified Low-Power Design Flow for Data-Dominated Multi-Media and Telecom Applications”, editor F. Catthoor, Kluwer Academic Publishers 2000, ISBN 0-7923-7947-0.
3. Zervas N.D., Soudris D., Theoharis S., Perakis M., Goutis C.E., “Power Management for Digital Receivers”, Chapter in “Unified Low-Power Design Flow for Data-Dominated Multi-Media and Telecom Applications”, editor F. Catthoor, Kluwer Academic Publishers 2000, pp. 135-157, ISBN 0-7923-7947-0.
4. Zervas N.D., Theoharis S., Perakis M., Goutis C.E. and Soudris D., “Run-Time Power Management for Low and Medium Bit-Rate Receivers”, Chapter in “Unified Low-Power Design Flow for Data-Dominated Multimedia and Telecom Applications”, editor F. Catthoor, Kluwer Academic Publishers 2000, ISBN 0-7923-7947-0.